The invention relates to Direct Memory Access (DMA) control, and in particular, to a DMA controller, to a computer system including a DMA controller and to a method of DMA control.
DMA controllers can be provided in computer systems to enable, for example, devices connected to an I/O bus, or the like, to make direct access to the memory and/or other resources of a processor of the computer system. The DMA controller could be integral with, or separate from, such an I/O device. DMA controllers can also find application in other configurations, for example for facilitating memory to memory transfers. The invention finds application generally to DMA controllers and methods of operation thereof.
By way of non-limiting example, therefore, one typical configuration of a computer system with a DMA controller can include a processor connected to memory via a processor bus. An I/O controller connected to the processor bus can form a bridge between the processor bus and a further bus, for example a bus (SBus) operable under a system bus protocol known as the xe2x80x98SBusxe2x80x99 protocol. A DMA controller can also be connected to the SBus and can provide a further bridge to an I/O bus to which I/O devices are connected. In normal operation, the processor writes to and reads from the memory. However, the direct memory access controller performs DMA operations to provide read and write access to the memory for I/O devices.
The DMA controller needs to receive DMA commands (also known as descriptors) from the processor to enable it to function. The DMA commands can, for example, specify a start address for Direct Virtual Memory Access (DVMA) and I/O bus accesses, and a transfer length up to a given maximum. It has been suggested to hold DMA commands in, for example, a control buffer in main memory, and then to transfer them to the DMA controller under the control of the processor. However, in such a configuration, the transfer of the DMA commands from the processor to the DMA controller can have non-negligible impact on performance of the system. This is due to the I/O traffic needed to provide handshaking over the bus or buses between the processor and the DMA controller in connection with the transfer of the DMA commands. Another problem with use of a command buffer is the addressing of the buffer for the addition to, and removal from, the command buffer of the DMA commands. This is a problem that is common to DMA controllers operable with command buffers.
An aim of the present invention is to provide a DMA controller, a system including such a DMA controller, and a method of operation of such a system, which mitigate the problems described above associated with the transfer of DMA commands to the DMA controller.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with one aspect of the invention, there is provided a direct memory access (DMA) controller for a computer system, which computer system includes a processor and a command buffer for holding a sequence of DMA commands. The DMA controller includes control logic and head and tail pointer registers for holding head and tail pointers for pointing to a head and tail, respectively, of a sequence of DMA commands in the command buffer. The control logic is responsive to the tail pointer in the tail register for accessing a DMA command to be transferred from the command buffer to the DMA controller.
By provision of the tail pointer in the DMA controller, the DMA controller is able directly to access DMA commands under its own control and without reference to the processor. The command buffer can be directly addressable by the processor for storing DMA commands in the command buffer. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer, which is held locally in the DMA controller. It is to be understood that the head pointer points to the head of a sequence of DMA commands in the command buffer (i.e. where DMA commands are added to the buffer by the processor) and the tail pointer points to the tail of the sequence of commands in the command buffer (i.e. where DMA commands are taken from the command buffer by the DMA controller). In this manner, the processor is able to buffer the DMA commands and then the DMA controller is able to access those commands at a convenient time, without needing to provide handshaking between the processor and the DMA controller for the transfer of the DMA commands.
Preferably, the command buffer is configured as a ring buffer, that is a buffer addressable by modulo-addressing. This facilitates the addressing of the buffer, as the pointers can be arranged automatically to return to the address at the beginning of the buffer when the end of the buffer address range is reached. In a particularly convenient manner the addressing is on the basis of a base address and offset, with the offset wrapping round, or returning, to a first predetermined value (e.g. 0) when a second predetermined value (e.g., n, where n is the size of the ring buffer) is reached. The use of modulo-addressing facilitates the separation of the control of the pointers between the processor and the DMA controller. In an embodiment, the processor can be responsible for updating the head pointer and the DMA controller can be responsible for updating the tail pointer.
In an embodiment of the invention, the control logic in the DMA controller is operable to compare the head and tail pointers in the head and tail registers, respectively. The control logic can be arranged to respond to the head and tail pointers being equivalent as indicative of the sequence of DMA commands actually containing no DMA commands (i.e., the command buffer is empty). In this case the DMA controller knows that it does not need to carry out a DMA operation to access the DMA commands from the command buffer. Here it is to be understood the reference to the head and tail pointers being xe2x80x9cequivalentxe2x80x9d refers to these pointers effectively pointing to the same DMA command buffer storage location within the command buffer. This can mean that the numerical values of the pointers are the same, or if different addressing modes are employed, that they have a predetermined relationship to one another.
In this embodiment of the invention, the control logic is operable to respond to non-equivalence of the head and tail pointers as indicative of at least one DMA command being in the sequence of DMA commands. In this case the DMA control logic uses the tail pointer in the tail register for accessing a DMA command to be transferred from the tail of the sequence of DMA commands in the command buffer to the DMA controller. The DMA controller is thereby able locally to determine whether DMA commands are available to be transferred from the command buffer to the DMA controller without needing to access the command buffer.
The DMA controller can further be operable to write a completion indicator to a location in the command buffer from which a direct memory access command has been read. This can be used to indicate which DMA commands have been completed.
The DMA controller can further be operable to update the tail pointer value following completion of a direct memory access command from a location in the command buffer.
In one particular embodiment of the invention the command buffer is provided in main memory and a first bus connects the processor to the memory. The processor is able directly to store DMA commands in the command buffer via the first bus using a mirror head pointer and mirror tail pointer held in a processor register or in memory, and to update the head pointer in the DMA controller. The DMA controller is connected either directly or indirectly to the first bus. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer held locally in the DMA controller. In this manner, the processor is able to buffer the DMA commands and then the DMA controller is able to access those commands at a convenient time, without needing to provide handshaking over the first bus between the processor and the DMA controller for the transfer of the DMA commands. The DMA controller can be connected to a second bus to which one or more DMA devices are also connected.
In another embodiment the DMA controller may be integral with an I/O device.
In a further embodiment, the DMA controller can integral with the processor. In such a case, the DMA command buffer could be held in internal processor storage, for example a special purpose buffer.
In accordance with another aspect of the invention there is provided a computer system including a processor, a command buffer for buffering a sequence of direct memory access (DMA) commands and a DMA controller, as set out above.
As described above, in one particular embodiment the command buffer can be configured in a memory, and a first bus can connect the processor to the memory. The processor can be operable to add DMA commands to the command buffer and to update the head pointer in the head register of the DMA controller. The DMA controller can be connected to a second bus to which one or more I/O devices are connected. Alternatively, the DMA controller can be integrated in an I/O device. In a further embodiment the DMA controller could be integral with the processor.
In a particular embodiment of the invention, a third bus is provided between the first bus and the DMA controller, an I/O control bridge being connected between the first and third buses and the DMA controller being connected between the third and second buses.
The DMA controller can be responsible for updating its own tail pointer in association with the completion of a DMA command from the command buffer. The processor can be responsible for updating the head pointer in the DMA controller in association with the storage of DMA commands in the command buffer. The processor can further be operable to maintain a mirror head pointer in a mirror head register, the processor being responsive to the mirror head pointer for adding DMA commands to the head of the command buffer.
The processor can maintain a mirror tail pointer in a register or memory, and update the mirror tail pointer from the DMA controller tail pointer only when the mirror tail pointer seems to indicate that no command buffer space is left. The likelihood is that by this time, the DMA controller will have advanced its own tail pointer, and the space will actually have become available. This minimizes processor reads of the DMA controller registers.
Although there is a bus overhead involved in updating the head register in the DMA controller, this is much less than the bus overhead associated with a transfer under processor control of the DMA commands from the processor to the DMA controller. This arises from a number of reasons, including the pointer being smaller than the DMA command and because a pointer does not need to be sent for each DMA command. In addition, the DMA controller is able to select when to download the DMA commands. Moreover, the separation of the control of the head and tail pointers facilitates efficient operation of the DMA controller. The addressing of the head and tail pointers is particularly efficient if modulo-addressing of the command buffer is used (e.g., with the command buffer configured as a ring buffer).
As well as, or instead of, being used for I/O transfers, the DMA controller can be used for memory to memory transfers.
In accordance with a further aspect of the invention, there is provided a method of controlling direct memory access (DMA) in a computer system including a processor, a command buffer for holding a sequence of DMA commands and a DMA controller. The method includes steps of:
the processor adding at least one DMA command to a head of the sequence of DMA commands in the command buffer; and
the DMA controller transferring a DMA command from a tail of the sequence of DMA commands in the command buffer by DMA using a tail pointer held in a tail register in the DMA controller.